AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 128

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

18.1
18.1.1
128
Interface Description
AT89LP51RD2/ED2/ID2 Preliminary
SPI Serial Clock (SCK)
The interconnection between master and slave devices with SPI is shown in
pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Serial Clock
(SCK), and Slave Select (SS). The MSTR bit in SPCON determines the directions of MISO and
MOSI. Also notice that MOSI connects to MOSI and MISO to MISO. By default SS is an input to
both master and slave devices. The master must drive the SS input of each slave device
independently.
Figure 18-2. SPI Master-Slave Interconnection
The location of the SPI pins is determined by the REMAP bit in SPSTA as shown in
W h e n R E M A P = 0 , t h e p i n s a r e l o c a t e d i n t h e s a m e l o c a t i o n s o n P o r t 1 a s t h e
AT89C51RD2/ED2/ID2. When REMAP = 1 the pins are shuffled on Port 1 to be compatible with
AT89S8253 and AT89LP6440. Note that the SPI-based In-System Programming (ISP) interface
always uses the REMAP = 1 pins regardless of the REMAP setting.
Table 18-1.
This signal is used to synchronize the data movement both in and out of the devices through
their MOSI and MISO lines. The SCK line is shared among all devices on the bus. It is driven by
the master for eight clock cycles to exchange one byte on the serial lines. The SCK pin is a clock
output in master mode and a clock input in slave mode. If multiple masters are present in a sys-
tem, only one should drive the SCK line at a time.
In master mode, the baud rate of SCK is determined by the SPR bits in SPCON. The SPR bits
select a value from a 7-bit prescaler on the system clock or the Timer 1 overflow. In slave mode
the clock rate is set by the master device; the slave need not
Name
SCK
MISO
MOSI
SS
MSB
Generator
Clock
Function
Serial Clock
Master In / Slave Out
Master Out / Slave In
Slave Select (Active-Low)
Serial Peripheral Interface Connections
8-Bit Shift Register
Master
MODF
LSB
GPIO
SSDIS
REMAP = 0
SS
MISO
MOSI
SCK
P1.6
P1.5
P1.7
P1.1
V
Pin Connection
CC
MISO
MOSI
SCK
SS
REMAP = 1
P1.7
P1.6
P1.5
P1.4
MSB
SSDIS
8-Bit Shift Register
MSTR = 1
Slave
OUT
OUT
IN
IN
Direction
Figure
3714A–MICRO–7/11
LSB
MSTR = 0
Table
. The four
OUT
IN
IN
IN
18-1.