AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 74

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

12.1.3
12.1.4
12.2
74
Port Analog Functions
AT89LP51RD2/ED2/ID2 Preliminary
Open-drain Output
Push-pull Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to V
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in
during Power-down (see
Power-down when configured in this mode.
Figure 12-4. Open-Drain Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. The push-pull port configuration is shown in
Figure 12-5. Push-pull Output
The AT89LP51RD2/ED2/ID2 incorporates two analog comparators and an 8-channel analog-to-
digital converter. In order to give the best analog performance and minimize power consump-
tion, pins that are being used for analog functions must have both their digital outputs and digital
inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as
described in
only mode after reset regardless of the state of the Tristate-Port Fuse.
Register
F rom P o r t
“Port Configuration” on page
F rom P o r t
Register
Figure
Figure
12-4. The input circuitry of P3.2, P3.3, P4.6 and P4.7 is not disabled
12-3) and therefore these pins should not be left floating during
Input
Data
PWD
71. The analog input pins will always default to input-
Input
Data
V
CC
PWD
Figure
P o r t
Pin
12-5.
P o r t
Pin
3714A–MICRO–711
DD
. The pull-