AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 98

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 17-4.
18. Dual Analog Comparators
98
SPSR Address = E8H
Not Bit Addressable
Symbol
SPIF
WCOL
MODF
TXE
SSIG
DISSO
ENH
Bit
AT89LP428/828
SPIF
Function
SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt
is generated if ESP = 1. The SPIF bit may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
Write Collision Flag. The WCOL bit is set by hardware if SPDR is written while the transmit buffer is full. The ongoing
transfer is not affected. WCOL may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
Mode Fault Flag. MODF is set by hardware when a master mode collision is detected (MSTR = 1, SSIG = 0 and SS = 0)
and an interrupt is generated if ESP = 1. MODF must be cleared by software.
Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte
to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.
Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSIG = 1, the
SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. When MSTR = 1 and SSIG = 0, SS is
monitored for master mode collisions. Setting SSIG = 1 will ignore collisions on SS. P1.4 may be used as a regular I/O
pin when SSIG = 1.
Disable slave output bit. When set, this bit causes the MISO pin to be tristated so that more than one slave device can
share the same interface without multiple SS lines. Normally, the first byte in a transmission could be the slave address
and only the selected slave should clear its DISSO bit.
TX Buffer Interrupt Enable. When ENH = 1, TXE will generate an SPI interrupt if ESP = 1. When ENH = 0, TXE does not
generate an interrupt.
7
SPSR – SPI Status Register
WCOL
The AT89LP428/828 provides two analog comparators. The analog comparators have the fol-
lowing features:
A block diagram of the dual analog comparators with relevant connections is shown in
18-1. Input options allow the comparators to function in a number of different configurations as
shown in
tive input is greater than the negative input. Otherwise, the output is a zero. Setting the CENA
(ACSRA.3) and CENB (ACSRB.3) bits enable Comparator A and B, respectively. The user must
also set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs
before using a comparator. When a comparator is first enabled, the comparator output and
6
• Internal 3-level Voltage Reference
• Multiple Shared Analog Input Channels
• Selectable Interrupt Conditions
• Hardware Debouncing Modes
– High- or Low-level
– Rising- or Falling-edge
– Output Toggle
Figure
MODF
5
18-3. Comparator operation is such that the output is a logic “1” when the posi-
TXE
4
–
3
SSIG
2
Reset Value = 0000 X000B
DISSO
1
ENH
0
3654A–MICRO–8/09
Figure