AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 103

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 18-2.
Notes:
3654A–MICRO–8/09
Symbol
CSB
[1 - 0]
CONB
CFB
CENB
CMB
[2 - 0]
ACSRB = 9FH
Not Bit Addressable
Bit
1. CONB must be cleared to 0 before changing CSB [1 - 0].
2. Debouncing modes require the use of Timer 1 to generate the sampling delay.
Function
Comparator B Positive Input Channel Select
Comparator B Input Connect. When CONB = 1, the analog input pins are connected to the comparator. When
CONB = 0 the analog input pins are disconnected from the comparator. CONB must be cleared to 0 before changing
CSB [1 - 0] or RFB [1 - 0].
Comparator B Interrupt Flag. Set when the comparator output meets the conditions specified by the CMB [2 - 0] bits and
CENB is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.
Comparator B Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and
prevent further events from setting CFB. When CENB = 1, the analog input pins, P2.4 - P2.7, have their digital inputs
disabled if they are configured in input-only mode.
Comparator B Interrupt Mode
CMB2
CSB1
ACSRB
CSB1
0
0
1
1
0
0
0
0
1
1
1
1
7
– Analog Comparator B Control and Status Register
CMB1
CSB0
0
1
0
1
0
0
1
1
0
0
1
1
CSB0
6
B+ Channel
AIN0 (P2.4)
AIN1 (P2.5)
AIN2 (P2.6)
AIN3 (P2.7)
CMB0
0
1
0
1
0
1
0
1
CONB
5
Interrupt Mode
Negative (Low) level
Positive edge
Toggle with debouncing
Positive edge with debouncing
Negative edge
Toggle
Negative edge with debouncing
Positive (High) level
(1)
CFB
4
(2)
CENB
3
(2)
(2)
CMB2
2
Reset Value = 1100 0000B
AT89LP428/828
CMB1
1
CMB0
0
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