AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 62

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

13.1
62
CCA Registers
AT89LP428/828
Timer 2 must be running (TR2 = 1) in order to perform captures or compares with the CCA.
However, when TR2 = 0 the external capture events will still set their associated flags and may
be used as additional external interrupts.
Figure 13-1. Compare/Capture Array Block Diagram
The Compare/Capture Array has five Special Function Registers: T2CCA, T2CCC, T2CCL,
T2CCH and T2CCF. The T2CCF register contains the interrupt flags for each CCA channel. The
CCA interrupt is a logic OR of the bits in T2CCF. The flags are set by hardware when a com-
pare/capture event occurs on the relevant channel and must be cleared by software. The
T2CCF bits will only generate an interrupt when the ECC bit (IE2.1) is set and the CIENx bit in
the associated channel’s CCCx register is set.
The T2CCC, T2CCL and T2CCH register locations are not true SFRs. These locations represent
access points to the contents of the array. Writes/reads to/from the T2CCC, T2CCL and T2CCH
locations will access the control, data low and data high bytes of the CCA channel currently
selected by the index in T2CCA. Channels currently not indexed by T2CCA are not accessible.
When writing to T2CCH, the value is stored in a shadow register. When T2CCL is written, the
16-bit value formed by the contents of T2CCL and the T2CCH shadow is written into the array.
Therefore, T2CCH must be written prior to writing T2CCL. All four channels use the same
T2CCH shadow register. If the value of T2CCH remains constant for multiple writes, there is no
need to update T2CCH between T2CCL writes. Every write to T2CCL will use the last value of
T2CCH for the upper data byte. It is not possible to write to the data register of a channel config-
ured for capture mode.
The configuration bits for each channel are stored in the CCCx registers accessible through
T2CCC. See
OSC
(P1.0) T2
Table 13-4 on page 64
÷TPS
T2CCA
C/T2 = 0
C/T2 =1
TR2
T2CCC
CCCC
CCCD
CCCA
CCCB
for a description of the CCCx register.
RCAP2L
T2CCL
CCAL
CCBL
CCCL
CCDL
TL2
RCAP2H
T2CCH
CCAH
CCBH
CCCH
CCDH
TH2
T2CCF
TF2
Timer 2 Interrupt
CCA Interrupt
CCA (P2.0)
CCB (P2.1)
CCC (P2.2)
CCD (P2.3)
3654A–MICRO–8/09