AT89LP428 Atmel Corporation, AT89LP428 Datasheet - Page 47

• Manufacturer Part Number: AT89LP428
• Manufacturer: Atmel Corporation

Specifications of AT89LP428

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 512
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 11-4.
11.5
3654A–MICRO–8/09
Symbol
PWM1EN
PWM0EN
PSC1
PSC0
TCONB = 91H
Not Bit Addressable
Bit
2-0
2-0
Pulse Width Modulation
Function
Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5).
Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4).
Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1. After reset PSC1 = 100B which
enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89S2051.
Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1. After reset PSC0 = 100B which
enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C52.
PWM1EN
TCONB
7
– Timer/Counter Control Register B
On the AT89LP428/828, Timer 0 and Timer 1 may be independently configured as 8-bit asym-
metrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN
bits in TCONB, respectively. In PWM mode the generated waveform is output on the timer's
input pin, T0 or T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0 (P3.4)
and T1 (P3.5) must be configured in an output mode. The Timer Overflow Flags and Interrupts
will continue to function while in PWM mode and Timer 1 may still generate the baud rate for the
UART. The timer GATE function also works in PWM mode, allowing the output to be halted by
an external input. Each PWM channel has four modes selected by the mode bits in TMOD.
An example waveform for Timer 0 in PWM mode 0 is shown in
counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is
set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low.
Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to
RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM
output low.
Figure 11-5. 8-bit Asymmetrical Pulse Width Modulation
PWM0EN
6
(P3.4)T0
FFH
RH0
00H
TH0
PSC12
5
PSC11
4
PSC10
3
TF0 Set
PSC02
2
Figure
Reset Value = 0010 0100B
AT89LP428/828
PSC01
1
11-5. TH0 acts as an 8-bit
PSC00
0
Time
47