AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 89

• Manufacturer Part Number: AT89C51AC3
• Manufacturer: Atmel Corporation

Specifications of AT89C51AC3

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Error Conditions
Mode Fault Error (MODF)
4383D–8051–02/08
The following flags in the SPSCR register indicate the SPI error conditions:
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device.
•
MODF is set to warn that there may be a multi-master conflict for system control. In this
case, the SPI system is affected in the following ways:
Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-
inal set state after the MODF bit has been cleared.
Figure 50. Mode Fault Conditions in Master Mode (Cpha =’1’/Cpol =’0’)
Note:
•
In slave mode, the MODF error is detected when SS goes high during a transmission.
A transmission begins when SS goes low and ends once the incoming SCK goes back
to its idle level following the shift of the eighteen data bit.
A MODF error occurs if a slave is selected (SS is low) and later unselected (SS is high)
even if no SCK is sent to that slave.
At any time, a ’1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance
state and internal state counter is cleared. Also, the slave SPI ignores all incoming SCK
clocks, even if it was already in the middle of a transmission. A new transmission will be
performed as soon as SS pin returns low.
Mode fault detection in Master mode:
–
–
–
Mode fault detection in Slave mode
An SPI receiver/error CPU interrupt request is generated
The SPEN bit in SPCON is cleared. This disables the SPI
The MSTR bit in SPCON is cleared
When SS is discarded (SS disabled) it is not possible to detect a MODF error in master
mode because the SPI is internally unselected and the SS pin is a general purpose I/O.
SCK cycle #
(from master)
MOSI
(from master)
MISO
(from slave)
SPI enable
SS
(slave)
SCK
SS
(master)
1
0
1
0
1
0
1
0
1
0
1
0
z
z
z
z
z
z
MODF detected
0
0
MSB
MSB
1
MODF detected
B6
B6
2
3
B5
0
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