AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet - Page 46

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AT89C51AC3

Manufacturer Part Number
AT89C51AC3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51AC3

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
2.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART
Watchdog
Yes

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Status of the Flash Memory
Selecting FM1
Loading the Column Latches
46
AT89C51AC3
Table 16. Programming Spaces
Notes:
The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
The flash programming process is launched the second machine cycle following the
sequence 5xh and Axh in FCON. Thus the FBUSY flag should be read by sofware not
during the insctruction after the 5xh, Axh sequence but the the second instruction after
the 5xh, Axh sequence in FCON (See next example). FBUSY is cleared when the pro-
gramming is completed.
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.
Any number of data from 1-byte to 128 Bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of Bytes in a page. Data written in the column latches do not have to be in consecutive
Extra Row
Hardware
Columns
Security
Latches
Reset
User
Byte
;*F*************************************************************************
;* NAME: launch_prog
;;***************************************************************************
launch_prog:
wait_busy:
1. The sequence 5xh and Axh must be executing without instructions between them
2. The sequence 5xh and Axh must be executed with the same FMOD0 FMOD1
3. Interrupts that may occur during programming time must be disabled to avoid any
MOV FCON, #050h
MOV FCON #0A0h ; Flash Write Sequence
NOP
MOV A,FCON
JB ACC.0,wait_busy
RET
otherwise the programming is not executed (see Flash Status Register)
configuration.
spurious exit of the programming mode.
FPL3:0
A
A
A
A
5
5
5
5
FPS
;Required time before reading busy flag
Write to FCON
X
X
X
X
X
X
X
X
FMOD1
0
0
0
0
1
1
1
1
FMOD0
0
0
1
1
0
0
1
1
Operation
No action
Write the column latches in user
space
No action
Write the column latches in extra row
space
No action
Write the fuse bits space
No action
Reset the column latches
4383D–8051–02/08

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