AT89C5131A-M Atmel Corporation, AT89C5131A-M Datasheet - Page 95
AT89C5131A-M
Manufacturer Part Number
AT89C5131A-M
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5130A-M.pdf
(188 pages)
2.AT89C5130A-M.pdf
(4 pages)
3.AT89C5130A-M.pdf
(34 pages)
Specifications of AT89C5131A-M
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART/USB
Watchdog
Yes
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19.3
19.3.1
4337K–USB–04/08
Functional Description
Operating Modes
Figure 19-2
Figure 19-2. SPI Module Block Diagram
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI module is made through one register:
Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
• The Serial Peripheral CONtrol register (SPCON)
• SPCON
• The Serial Peripheral STAtus register (SPSTA)
• The Serial Peripheral DATa register (SPDAT)
SPR2
1
SPI Interrupt Request
shows a detailed structure of the SPI module.
SPR1
1
Clock
Divider
SPR0
FCLK PERIPH
SPR2
1
/128
/16
/32
/64
SPEN
/8
/4
Clock
Select
SSDIS
MSTR
SPIF
Clock Rate
Don’t Use
Receive Data Register
CPOL
WCOL
7
Shift Register
Internal Bus
6
SPI
Control
CPHA
5
SSERR
4
3
AT89C5130A/31A-M
SPR1
2
Clock
Logic
SPCON
1
SPDAT
MODF
0
SPR0
-
Baud Rate Divisor (BD)
M
Pin
Control
Logic
S
-
No BRG
-
SPSTA
-
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
95
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