AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 820

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

AT32UC3L016/32/64
Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of
write value.
Fix/Workaround
For every interrupt except BODDET, SM33DET, and VREGOK the PCLKSR register can be
read to detect new interrupts. BODDET, SM33DET and VREGOK interrupts will not be gen-
erated if they occur whilst writing to the ICR register.
FINE value for DFLL is not correct when dithering is disabled
In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the
value written to the DFLL0CONF.FINE field. The value used by the DFLL DAC is
DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001 or 0x002 the
value used by the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively.
Fix/Workaround
Write the desired value added by two to the DFLL0CONF.FINE field.
BODVERSION register reads 0x100
The BODVERSION register reads 0x100 instead of 0x101
Fix/Workaround
None.
VREGCR.DEEPMODEDISABLE bit is not readable
VREGCR.DEEPMODEDISABLE bit is not readable.
Fix/Workaround
None.
DFLL step size should be seven or lower when below 30MHz
If max step size is above seven, the DFLL might not lock at the correct frequency if the tar-
get frequency is below 30MHz.
Fix/Workaround
If the target frequency is below 30MHz, use a max step size (DFLL0MAXSTEP.MAXSTEP)
of seven or lower.
Generic clock sources are kept running in sleep modes
If a clock is used as a source for a generic clock when going to a sleep mode where clock
sources are stopped, the source of the generic clock will be kept running. Please refer to
Power Manager chapter for details about sleep modes.
Fix/Workaround
Disable generic clocks before going to sleep modes where clock sources are stopped to
save power.
DFLL clock is unstable with a fast reference clock
The DFLL clock can be unstable when a fast clock is used as a reference clock in closed
loop mode.
Fix/Workaround
Use the 32KHz crystal oscillator clock, or a clock with a similar frequency, as DFLLIF refer-
ence clock.
DFLLIF indicates coarse lock too early
The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it
later.
Fix/Workaround
Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
DFLLIF dithering does not work
820
32099G–06/2011