AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 196

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.7.4
13.5.8
13.5.8.1
13.5.8.2
32099G–06/2011
3.3 V Supply Monitor (SM33)
POR33 control
Register protection
Operating modes
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to VREGCR.CALIB or altering the values for the VREGIFB flash
fuses.
If the Flash Calibration Done (FCD) bit in the VREGCR is zero at any reset except for POR and
POR33, then the flash calibration will be redone and the VREGCR.FCD bit will be set before pro-
gram execution starts in the CPU. If the VREGCR.FCD is one then the calibration will not be
changed during a reset.
VREGCR includes control bits for the Power-On Reset 3.3V (POR33) detector that monitors the
VDDIN voltage. The POR33 is on by default but can be turned off by software to reduce power
consumption. The 3.3V Supply Monitor (SM33) can then be used to monitor the VDDIN power
supply.
Disabling the POR33 is done by writing a zero to the POR33 Enable bit (VREGCR.POR33EN).
Because of internal synchronisation, the POR33 is not immediately enabled or disabled. The
actual state of the POR33 can be read from the POR33 Status bit (VREGCR.POR33STATUS).
The RC32K oscillator must be enabled to disable the POR33. Once the POR33 has been dis-
abled, the RC32K oscillator can be turned off again.
T h e P O R 3 3 r e s e t c a n b e i g n o r e d b y w r i t i n g a o n e i n t h e P O R 3 3 M a s k b i t
(VREGCR.POR33MASK). Because of internal synchronization, the masking is not immediately
effective, so software should wait for the VREGCR.POR33MASK to be read as a one before
assuming masking is effective. To avoid spurious resets, it is mandatory to mask the POR33
reset when enabling or disabling it.
Rev: 1.0.0.0
The 3.3V supply monitor is a specific voltage detector for the VDDIN voltage. It will indicate if the
VDDIN voltage is above the minimum required input voltage for the voltage regulator . The user
can choose to generate either a reset or an interrupt when the VDDIN voltage drops below this
limit. If reset is selected, this will generate a POR reset.
Please refer to Electrical Characteristics for parametric details.
To prevent unexpected writes to SM33 register due to software bugs, write access to this regis-
ter is protected by a locking mechanism. For details please refer to the UNLOCK register
description.
To prevent further modifications by software, the content of the register can be set as read-only
by writing a one to the Set ForeVer bit (SM33.SFV). Once this bit is set, software can not change
the SM33 content until a POR or POR33 reset is applied.
The SM33 is disabled by default and is enabled by writing to the Supply Monitor Control field in
the SM33 control register (SM33.CTRL).
AT32UC3L016/32/64
196