AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 245

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.7
32099G–06/2011
Module Configuration
The specific configuration for each SCIF instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 13-7.
Table 13-8.
Table 13-9.
In AT32UC3L, there are six generic clocks. These are allocated to different functions as shown
in
Table 13-10. Generic Clock Allocation
Module Name
SCIF
Clock number
Table
STARTUP
GAIN[1:0]
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
13-10. Note that only GCLK4-0 are routed out.
MODULE Clock Name
Oscillator Startup Time
Oscillator
Number of System RC
oscillator clock cycle
0
64
128
2048
4096
8192
16384
Reserved
Oscillator is used with gain G0 (XIN from 0.45 MHz to 12.0 MHz)
Oscillator is used with gain G1 (XIN from 12.0 MHz to 16.0 MHz)
Oscillator is used with gain G2 (XIN equals 16.0 MHz. Used for e.g. increasing S/N
ratio, better drive strength for high ESR crystals)
Oscillator is used with gain G3 (XIN equals 16.0 MHz. Used for e.g. increasing S/N
ratio, better drive strength for high ESR crystals)
Clock Name
CLK_SCIF
Function
DFLLIF main reference and GCLK0 pin
(CLK_DFLLIF_REF)
DFLLIF dithering and ssg reference and GCLK1 pin
(CLK_DFLLIF_DITHER)
AST and GCLK2 pin
Gain Settings
Approximative Equivalent time
(RCSYS = 115 kHz)
0
560 us
1.1 ms
18 ms
36 ms
71 ms
142 ms
Reserved
Description
Clock for the SCIF bus interface
AT32UC3L016/32/64
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