AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 198

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.11
13.5.12
13.5.13
32099G–06/2011
Backup Registers (BR)
32kHz RC Oscillator (RC32K)
Generic Clocks
The oscillator is automatically disabled in certain sleep modes to reduce power consumption, as
described in the Power Manager chapter.
Rev: 1.0.0.1
Four 32-bit backup registers are available to store values when the chip is in Shutdown mode.
These registers will keep their content even when the VDDCORE and VDDIO supplies are
removed. The backup registers can be accessed by reading and writing the BR0, BR1, BR2,
and BR3 registers.
After writing to one of the backup registers the user must wait until the Backup Register Interface
Ready (BRIFARDY) bit in PCLKSR is set before writing to another backup register. Writes to the
backup register while BRIFARDY is zero will be discarded. An interrupt can be generated on a
zero-to-one transition on BRIFARDY.
After powering up the device the Backup Register Interface Valid (BRIFAVALID) bit in PCLKSR
is cleared, indicating that the contents of the backup registers has not been written and contains
the reset value. After writing one of the backup registers the BRIFAVALID bit is set. During
writes to the backup registers (when BRIFARDY is zero) BRIFAVALID will be zero. If a reset
occurs when BRIFRDY is zero, BRIFAVALID will be cleared after the reset, indicating that the
contents of the backup registers are not valid. If BRIFARDY was one when the reset occurred,
BRIFAVALID will be one and the contents are the same as before the reset.
The user must ensure that BRIFAVALID and BRIFARDY are both set before reading the backup
register values.
Rev: 1.0.0.0
The RC32K can be used as source for the generic clocks, as described in The Generic Clocks
section.
The 32 kHz RC oscillator (RC32K) is forced on after reset, and output on PA20. The clock is
available on the pad until the PPCR.RC32OUT bit in the Power Manager has been cleared or a
different peripheral function has been chosen on port PA20 (port PA20 will start with peripheral
function “F” by default). Note that the forcing will only enable the clock output. To be able to use
the RC32K normally the oscillator must be enabled as described below.
The oscillator is enabled by writing a one to the Enable bit (EN) bit in the 32 kHz RC Oscillator
Configuration Register (RC32KCR) and disabled by writing a zero to RC32KCR.EN. The oscilla-
tor is also automatically enabled when the sampling mode is requested for the SM33. In this
case, writing a zero to RC32KCR.EN will not disable the RC32K until the sampling mode is no
longer requested.
Rev: 1.0.0.0
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that
can provide a wide range of accurate clock frequencies.
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