AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 160

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.6.6.1
12.6.6.2
12.6.7
12.6.8
32099G–06/2011
Clock Failure Detector
Interrupts
Power-On Detector
External Reset
Depending on the reset source, when a Reset occurs, some parts of the device are not always
reset. Only the Power On Reset (POR) will force a whole device reset. Refer to the table in the
Module Configuration section at the end of this chapter for further details. The latest reset cause
can be read in the RCAUSE register, and can be read during the applications boot sequence in
order to determine proper action.
The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the
device is powered on. The reset is active until the supply voltage from the linear regulator is
above the power-on threshold level. This reset will be re-activated if the voltage drops below the
power-on threshold level. See Electrical Characteristics for parametric details.
The external reset detector monitors the RESET_N pin state. By default, a low level on this pin
will generate a reset.
This mechanism automatically switches the main clock source to the safe RCSYS clock when
the main clock source fails. This may happen when an external crystal is selected as a source
for the main clock and the crystal is not mounted on the board. The main clock is compared with
RCSYS, and if no rising edge of the main clock is detected during one RCSYS period, the clock
is considered to have failed.
The detector is enabled by writing a one to the Clock Failure Detection Enable bit in the Clock
Failure Detector Control Register (CFDCTRL.CFDEN). As soon as the detector is enabled, the
clock failure detector will monitor the divided main clock. Note that the detector does not monitor
if RCSYS is the source of the main clock, or if the main clock is temporarily not available
(startup-time after a wake-up, switching timing etc.), or in sleep mode where the main clock is
driven by the RCSYS (Stop and DeepStop mode). When a clock failure is detected, the main
clock automatically switches to the RCSYS clock and the Clock Failure Detected (CFD) interrupt
is generated if enabled. The MCCTRL register is also changed by hardware to indicate that the
main clock comes from RCSYS.
The PM has a number of interrupts:
• AE: Access Error, set if a lock protected register is written to without first being unlocked.
• CKRDY: Clock Ready, set when new CKSEL settings have taken effect.
• CFD: Clock Failure Detected, set if the system detects that the main clock is not running.
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