AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 984

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatically update by setting the
2. Define the synchronous channels by the SYNCx bits in the SCM register.
3. Define the update period by the UPR field in the SCUP register.
4. Define when the WRDY bit and the corresponding PDCA transfer request must be set
5. Define the PDCA transfer settings for the duty-cycle values and enable it in the PDCA
6. Enable the synchronous channels by writing CHID0 in the ENA register.
7. If an update of the period value and/or of the dead-time values is required, write regis-
8. Write UPDULOCK to one in SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At
10. If an update of the update period value is required, check first that write of a new update
11. Write register that need to be updated (SCUPUPD).
12. The update of this registers will occur at the next PWM period of the synchronous chan-
13. Check the end of the PDCA transfer with the Transfer Complete bit in the PDCA status
UPDM field to 2 in the SCM register.
in the update period by the PTRM bit and the PTRCS field in the SCM register (at the
end of the update period or when a comparison matches).
registers
ters that need to be updated (CPRDUPDx, DTUPDx), else go to
this moment the UPDULOCK bit is reset, go to
value is possible by polling the WRDY bit (or by waiting for the corresponding interrupt)
in the ISR2 register, else go to
nels when the Update Period is elapsed. Go to
register. If the transfer is ended define a new PDCA transfer in the PDCA registers, for
new duty-cycle values. Go to
Step 5.
Step 13.
Step 7.
Step 10.
for new values.
for new values.
Step 10.
AT32UC3C
984