AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 814

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.8.2
Name:
Access Type:
Offset:
Reset Value:
The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK,
and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to dis-
able the IISC before writing a new value into MR.
• IWS24: IWS TDM Slot Width
• IMCKMODE: Master Clock Mode
• IMCKFS: Master Clock to fs Ratio
Table 30-4.
32117C–AVR-08/11
fs Ratio
128 fs
192fs
16 fs
32 fs
64 fs
48fs
96fs
IWS24
31
23
15
7
-
0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit
1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit
Refer to
0: No Master Clock generated (generic clock is used as ISCK output)
1: Master Clock generated (generic clock is used as IMCK output)
Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to
Clock and Word Select Generation” on page 806
Master Clock frequency is 8*(NBCHAN+1)*(IMCKFS+1) times the sample rate, i.e. IWS frequency:
Mode Register
FORMAT
2 channels
TDMFS
Master Clock to Sampling Frequency (fs) Ratio
11
Table 30-2, “Slot Length,” on page
0
1
2
3
5
7
IMCKMODE
TXSAME
30
22
14
MR
Read/Write
0x04
0x00000000
6
4 channels
0
1
2
3
5
-
-
IMCKFS
TXDMA
29
21
13
5
-
-
6 channels
0
1
3
-
-
-
-
807.
TXMONO
8 channels
28
20
12
and
4
-
0
1
2
Table 30-2, “Slot Length,” on page
-
-
-
-
DATALENGTH
27
19
11
3
-
IMCKFS
RXLOOP
26
18
10
2
807.
NBCHAN
RXDMA
25
17
9
1
-
Section 30.6.6 ”Serial
AT32UC3C
RXMONO
MODE
24
16
8
0
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