AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 334

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.6.7.4
Figure 18-29. NWAIT Latency
32117C–AVR-08/11
nternally synchronized
NWAIT signal
A[AD_MSB:2]
NBS0, NBS1,
CLK_SMC
A0, A1
NWAIT
NWAIT latency and read/write timings
NRD
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the two cycles of resynchronization
plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the
NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated
on
When the MODE.EXNWMODE field is enabled (ready or frozen), the user must program a pulse
length of the read and write controlling signal of at least:
Figure 18-29 on page
4
minimal pulse length
NWAIT latency 2 cycle resynchronization
3
Minimal pulse length
334.
2
EXNWMODE = 2 or 3
READMODE = 1 (NRD controlled)
NRDPULSE = 5
=
Read cycle
NWAIT latency
1
0
+
2 synchronization cycles
0
Wait STATE
0
AT32UC3C
+
1 cycle
334