AT32UC3C2512C Atmel Corporation, AT32UC3C2512C Datasheet - Page 1052

• Manufacturer Part Number: AT32UC3C2512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 34-6. PC reset by QEPI signal (TOP.PCTOP = 79, CF.IDXPHS =”00”, CF.IDXE = “1”)
34.6.1.8
34.6.1.9
34.6.2
34.6.2.1
32117C–AVR-08/11
Advanced Operation
Quadrature frequency
Disabling the QDEC
Compare register
IDXERR
QPulse
QEPA
QEPB
QEPI
The CLK_QDEC clock frequency must be at least two times the QEPA and QEPB frequency as
these signals are synchronized to the CLK_QDEC clock. To get the maximum available fre-
quency on QEPA/QEPB signals, the filter on inputs should be bypassed.
For a 33 MHz peripheral bus clock the maximum QEPA frequency is 16.5 MHz. For a wheel with
8192 lines the maximum rotational speed supported by QDEC is 16.5MHz / 8192 = 2014 rps =
120 849 rpm.
The QDEC is disabled by writing a zero to CTRL.CLKEN.
The Compare register (CMP) is used to generate an interrupt and a peripheral event when the
CNT register reaches the value defined in CMP.
If RC compare is enabled (CF.RCCE is one), a compare match occurs when RC is equal to
RCCMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
If the PC compare is enabled (CF.PCCE is one), a compare match occurs when the PC is equal
to PCCMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
If both RC compare and PC compare are enabled, a compare match occurs when CNT is equal
to CMP. A peripheral event is generated and the CMP interrupt line is set if enabled.
The compare peripheral event should be mapped through the PEVC to another peripheral.
RC
PC
72
73
0
74
75
0
1
2
1
3
2
1
0
79
0
78
77
AT32UC3C
1052