AT32UC3C064C Atmel Corporation, AT32UC3C064C Datasheet - Page 485

• Manufacturer Part Number: AT32UC3C064C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C064C

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.8
32117C–AVR-08/11
Module Configuration
The specific configuration for each GPIO instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager
chapter for details.
Table 23-3.
Table 23-4.
Table 23-5.
The reset values for all GPIO registers are zero, with the following exceptions:
Table 23-6.
Feature
Number of GPIO ports
Number of peripheral functions
Pin Function
Pull-up
Pull-down
Drive strength
Slew rate
Open Drain
Bus keeper
Module name
GPIO
Port
0
0
0
0
0
0
0
0
0
0
0
Module Configuration
Implemented Pin Functions
Module Clock Name
Register Reset Values
Register
GPER
PMR0
PMR1 - PMR2
ODER - OVR
PUER
PDER
IER - IMR0 - IMR1 - IFR
GFER
ODCR0
LOCK
PARAMETER
Clock Name
CLK_GPIO
Implemented
Yes
Yes
Yes
No
No
No
GPIO
4
4
Notes
Controlled by PUER or peripheral
Controlled by PDER
Writing to ODCR0 control the drive strength of the pads
Writing to ODCR1 has no effect
OSRRn registers are not implemented
ODMERn registers are not implemented
Setting {PUER, PDER} to 0x3 in a pin does not enable
the bus keeper on this pin
Reset Value
0x3FF9FFFF
0x00000001
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x3FF9FFFF
0x00000000
0x00000000
0x3FF9FFFF
Description
Peripheral Bus clock from the PBA clock domain
AT32UC3C
485