AT32UC3C064C Atmel Corporation, AT32UC3C064C Datasheet - Page 137

• Manufacturer Part Number: AT32UC3C064C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C064C

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5.2.3
9.5.3
9.5.3.1
32117C–AVR-08/11
Interrupts
Calendar operation
Periodic interrupt
The AST can generate five separate interrupt requests:
This allows the user to allocate separate handlers and priorities to the different interrupt types.
The generation of the PER interrupt is described in
ALARM interrupt is described in
ter overflows, or when the alarm value is reached, if the Clear on Alarm bit in the Control
Register is one. The CLKREADY interrupt is generated when SR.CLKBUSY has a 1-to-0 transi-
tion, and indicates that the clock synchronization is completed. The READY interrupt is
generated when SR.BUSY has a 1-to-0 transition, and indicates that the synchronization
described in
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one to the corresponding bit in the Status Clear Register (SCR).
The AST interrupts can wake the CPU from any sleep mode where the source clock and the
interrupt controller is active.
The AST can generate periodic interrupts. If the PERn bit in the Interrupt Mask Register (IMR) is
one, the AST will generate an interrupt request on the 0-to-1 transition of the selected bit in the
• OVF: OVF
• PER: PER0, PER1
• ALARM: ALARM0, ALARM1
• CLKREADY
• READY
When the CAL bit in the Control Register is one, the counter operates in calendar mode.
Before this mode is enabled, the prescaler should be set up to give a pulse every second.
The date and time can then be read from or written to the Calendar Value (CALV) register.
Time is reported as seconds, minutes, and hours according to the 24-hour clock format.
Date is the numeral date of month (starting on 1). Month is the numeral month of the year (1
= January, 2 = February, etc). Year is a 6-bit field counting the offset from a software-defined
leap year (e.g. 2000). The date is automatically compensated for leap years, assuming
every year divisible by 4 is a leap year.
All peripheral events and interrupts work the same way in calendar mode as in counter
mode. However, the Alarm Register (AR) must be written in time/date format for the alarm to
trigger correctly.
Section 9.5.7
is completed.
Section
9.5.3.2. The OVF interrupt is generated when the coun-
Section
9.5.3.1., and the generation of the
AT32UC3C
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