AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 54

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AT32UC3B1128

Manufacturer Part Number
AT32UC3B1128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3B1128

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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6.2.1.3
6.2.1.4
6.2.1.5
6.2.1.6
6.2.2
6.2.2.1
54
AVR32
MPU exception handling
MPU Cacheable Register A / B- MPUCRA / MPUCRB
MPU Bufferable Register A / B- MPUBRA / MPUBRB
MPU Access Permission Register A / B - MPUAPRA / MPUAPRB
MPU Control Register - MPUCR
ITLB Protection Violation
The MPUCR registers have one bit per region, indicating if the region is cacheable. If the corre-
sponding bit is set, the region is cacheable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUCR registers.
The MPUBR registers have one bit per region, indicating if the region is bufferable. If the corre-
sponding bit is set, the region is bufferable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUBR registers.
The MPUAPR registers indicate the access permissions for each region. The MPUAPR is writ-
ten to 0 upon reset. The possible access permissions are shown in
Table 6-3.
The MPUCR controls the operation of the MPU. The MPUCR has only one field:
This chapter describes the exceptions that can be signalled by the MPU.
An ITLB protection violation is issued if an instruction fetch violates access permissions. The vio-
lating instruction is not executed. The address of the failing instruction is placed on the system
stack.
AP
B’0000
B’0001
B’0010
B’0011
B’0100
B’0101
B’0110
B’0111
B’1000
B’1001
B’1010
Other
• E - Enable. If set, the MPU address checking is enabled. If cleared, the MPU address
checking is disabled and no exceptions will be generated by the MPU.
Access permissions implied by the APn bits
Privileged mode
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
Read / Write
Read / Write / Execute
Read / Write
Read / Write
None
UNDEFINED
Unprivileged mode
None
None
None
None
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
None
UNDEFINED
Table 6-3 on page
32000D–04/2011
54.

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