AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 229

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AT32UC3B1128

Manufacturer Part Number
AT32UC3B1128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3B1128

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32000D–04/2011
MTSR – Move to System Register
Architecture revision:
Architecture revision1 and higher.
Description
The instruction copies the value in the specified register to the specified system register. Note
that special timing concerns must be considered when operating on the system registers, see
the Implementation Manual for details.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Note:
Some system registers are implementation defined. If writing a system register that does not
exist, or to a register that is read only, the instruction is executed but no registers are updated.
With the exception of accessing the JECR and JOSP system registers, this instruction can only
be executed in a privileged mode. Execution from any other mode will trigger a Privilege Viola-
tion exception. JECR and JOSP can be accessed from all modes with this instruction.
The instruction mtsr JOSP, Rx must be used with care. The programmer must ensure that no
change of flow instruction nor an INCJOSP instruction follows mtsr JOSP, Rx within a number of
instructions. This number of cycles is implementation defined. It should also be noted, that this is
true even if the instructions are not to be executed. For instance the sequence
31
1
15
0
SystemRegister[SystemRegisterAddress << 2] ← Rs;
mtsr
SystemRegisterAddress ∈ {0, 4, 8, ..., 1020}
Q:
V:
N:
Z:
C:
mtsr JOSP, Rx
retj
incjosp
1
0
1
0
SystemRegisterAddress, Rs
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
0
0
0
0
0
0
1
0
8
1
0
7
1
0
System Register Ad-
1
20
1
19
Rs
AVR32
0
16
229

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