AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 18
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AT32UC3B1128
Manufacturer Part Number
AT32UC3B1128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B1128-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 18 of 377
- Download datasheet (5Mb)
18
CPUCR - CPU Control Register
ECR - Exception Cause Register
RSR_SUP, RSR_INT0, RSR_INT1, RSR_INT2, RSR_INT3, RSR_EX, RSR_NMI - Return Status Registers
RSR_DBG - Return Status Register for Debug Mode
RAR_SUP, RAR_INT0, RAR_INT1, RAR_INT2, RAR_INT3, RAR_EX, RAR_NMI - Return Address Registers
RAR_DBG - Return Address Register for Debug Mode
JECR - Java Exception Cause Register
JOSP - Java Operand Stack Pointer
AVR32
should be written to zero, making ACBA word aligned. Failing to do so may result in erroneous
behaviour.
Register controlling the configuration and behaviour of the CPU. The behaviour of this register is
IMPLEMENTATION DEFINED. An example of a typical control bit in the CPUCR is an enable bit
for branch prediction.
This register identifies the cause of the most recently executed exception. This information may
be used to handle exceptions more efficiently in certain operating systems. The register is
updated with a value equal to the EVBA offset of the exception, shifted 2 bit positions to the
right. Only the 9 lowest bits of the EVBA offset are considered. As an example, an ITLB miss
jumps to EVBA+0x50. The ECR will then be loaded with 0x50>>2 == 0x14. The ECR register is
not loaded when an scall, Breakpoint or OCD Stop CPU exception is taken. Note that for inter-
rupts, the offset is given by the autovector provided by the interrupt controller. The resulting ECR
value may therefore overlap with an ECR value used by a regular exception. This can be
avoided by choosing the autovector offsets so that no such overlaps occur.
If a request for a mode change, for instance an interrupt request, is accepted when executing in
a context C, the Status Register values in context C are automatically stored in the Return Sta-
tus Register (RSR) associated with the interrupt context I. When the execution in the interrupt
state I is finished and the rets / rete instruction is encountered, the RSR associated with I is cop-
ied to SR, and the execution continues in the original context C.
When Debug mode is entered, the status register contents of the original mode is automatically
saved in this register. When the debug routine is finished, the retd instruction copies the con-
tents of RSR_DBG into SR.
If a request for a mode change, for instance an interrupt request, is accepted when executing in
a context C, the re-entry address of context C is automatically stored in the Return Address Reg-
ister (RAR) associated with the interrupt context I. When the execution in the interrupt state I is
finished and the rets / rete instruction is encountered, a change-of-flow to the address in the
RAR associated with I, and the execution continues in the original context C. The calculation of
the re-entry addresses is described in
When Debug mode is entered, the Program Counter contents of the original mode is automati-
cally saved in this register. When the debug routine is finished, the retd instruction copies the
contents of RAR_DBG into PC.
This register contains information needed for Java traps, see AVR32 Java Technical Reference
Manual for details.
This register holds the Java Operand Stack Pointer. The register is initialized to 0 at reset.
Section 8. “Event Processing” on page
63.
32000D–04/2011
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