AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 48

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AT32UC3B1128

Manufacturer Part Number
AT32UC3B1128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3B1128

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
48
AVR32
MMU exception handling
ITLB / DTLB Multiple Hit
ITLB / DTLB Miss
ITLB / DTLB Protection Violation
This chapter describes the software actions that must be performed for MMU-related excep-
tions. The hardware actions performed by the exceptions are described in detail in
“Description of events in AVR32A” on page
If multiple matching entries are found when searching the ITLB or DTLB, this exception is
issued. This situation is a critical error, since memory consistency can no longer be guaranteed.
The exception hardware therefore jumps to the reset vector, where software should execute the
required reset code. This exception is a sign of erroneous code and is not normally generated.
The software handler should perform a normal system restart. However, debugging code may
be inserted in the handler.
This exception is issued if no matching entries are found in the TLBs, or when a matching entry
is found with the Valid bit cleared. The same actions must be performed for both exceptions, but
DTLB entries contains more control bits than the ITLB entries.
This exception is issued if the access permision bits in the matching TLB entry does not match
the privilege level the CPU is currently executing in. The exception is also issued if the MMU is
disabled or absent and non-translated areas are accessed with illegal access rights. The same
actions must be performed for both exceptions, but DTLB entries contains more control bits than
the ITLB entries.
Software must examine the TLBEAR and TLBEHI registers in order to identify the instruction
and process that caused the error. Corrective measures like terminating the process must then
be performed before returning to normal execution with rete.
1. Examine the TLBEAR and TLBEHI registers in order to identify the page that caused
2. Use the fetched page table entry to update the necessary bits in PTEHI and PTELO.
3. The TLBEHI[I] register is updated by hardware to indicate if it was a ITLB or a DTLB
4. Execute the tlbw instruction in order to update the TLB entry.
5. Finish the exception handling and return to the application by executing the rete
the fault. Use this to index the page table pointed to by PTBR and fetch the desired
page table entry.
The following bits must be updated, not all bits apply to ITLB entries: V, PFN, C, G, B,
AP[2:0], SZ[1:0], W, D.
miss. The MMUCR[IRP] and MMUCR[DRP] pointers may be updated in an IMPLE-
MENTATION DEFINED way in order to select which TLB entry to replace. The software
may override this value by writing a value directly to MMUCR[IRP] or MMUCR[DRP],
depending on which TLB to update.
instruction.
68.
Section 8.3.1
32000D–04/2011

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