AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 31

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7. Memories
7.1
7.2
32059L–AVR32–01/2012
Device
Start Address
Size
Embedded Memories
Physical Memory Map
AT32UC3B0512
AT32UC3B1512
AT32UC3B0256
AT32UC3B1256
AT32UC3B0128
AT32UC3B1128
AT32UC3B064
AT32UC3B164
•
•
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical
address space is mapped as follows:
Table 7-1.
Internal High-Speed Flash
Internal High-Speed SRAM, Single-cycle access at full speed
– 512KBytes (AT32UC3B0512, AT32UC3B1512)
– 256 KBytes (AT32UC3B0256, AT32UC3B1256)
– 128 KBytes (AT32UC3B0128, AT32UC3B1128)
– 64 KBytes (AT32UC3B064, AT32UC3B164)
– 96KBytes ((AT32UC3B0512, AT32UC3B1512)
– 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128)
– 16KBytes (AT32UC3B064 and AT32UC3B164)
• - 0 Wait State Access at up to 30 MHz in Worst Case Conditions
• - 1 Wait State Access at up to 60 MHz in Worst Case Conditions
• - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations,
• - 100 000 Write Cycles, 15-year Data Retention Capability
• - 4 ms Page Programming Time, 8 ms Chip Erase Time
• - Sector Lock Capabilities, Bootloader Protection, Security Bit
• - 32 Fuses, Erased During Chip Erase
• - User Page For Data To Be Preserved During Chip Erase
hiding penalty of 1 wait state access
0x0000_0000
Embedded
96 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
AT32UC3B Physical Memory Map
SRAM
0x8000_0000
512 Kbytes
256 Kbytes
128 Kbytes
Embedded
64 Kbytes
Flash
0xD000_0000
USB Data
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0xFFFF_0000
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Bridge A
HSB-PB
0xFFFE_0000
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Bridge B
HSB-PB
31