AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 883

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32. Advanced Encryption Standard (AES)
32.1
32.2
32.3
32.3.1
32072G–11/2011
Features
Overview
Product Dependencies
Power Management
Rev: 1.2.3.1
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The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Infor-
mation Processing Standard) Publication 197 specification.
The AES supports all five confidentiality modes of operation for symmetrical key block cipher
algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-
38A Recommendation. It is compatible with all these modes via DMA Controller, minimizing pro-
cessor intervention for large buffer transfers.
The 128-bit/192-bit/256-bit key is stored in write-only four/six/eight 32-bit KEY Word Registers
(KEYWnR) which are all write-only registers.
The 128-bit input data and initialization vector (for some modes) are each stored in 32-bit Input
Data Registers (IDATAnR) and in Initialization Vector Registers (VnR) which are all write-only
registers.
As soon as the initialization vector, the input data and the key are configured, the encryp-
tion/decryption process may be started. Then the encrypted/decrypted data is ready to be read
out on the four 32-bit Output Data Registers (ODATAnR) or through the DMA Controller.
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables clocks used by the AES, the AES will stop function-
ing and resume operation after the system wakes up from sleep mode.
Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
128-bit/192-bit/256-bit cryptographic key
12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit
cryptographic key
Support of the five standard modes of operation specified in the NIST Special Publication 800-
38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques:
8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode
Last output data mode allows optimized Message Authentication Code (MAC) generation
Hardware counter measures against differential power analysis attacks
Connection to DMA Controller capabilities optimizes data transfers for all operating modes
– Electronic Code Book (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
– Counter (CTR)
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