AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 329

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.1.2
32072G–11/2011
Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10)
4. After the DMACA selected channel has been programmed, enable the channel by writ-
5. Source and destination request single and burst DMA transactions to transfer the block
6. Once the transfer completes, hardware sets the interrupts and disables the channel. At
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as block descriptors) in mem-
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx according to Row 1 as shown in
d. Write the control information for the DMA transfer in the CTLx register for channel
– i. Set up the transfer type (memory or non-memory peripheral for source and
– ii. Set up the transfer characteristics, such as:
e. Write the channel configuration information into the CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
– ii. If the hardware handshaking interface is activated for the source or destination
ing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is
enabled.
of data (assuming non-memory peripherals). The DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
this time you can either respond to the Block Complete or Transfer Complete interrupts,
or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to
detect when the transfer is complete.
ory. Write the control information in the LLI.CTLx register location of the block
descriptor for each LLI in memory (see
example, in the register, you can program the following:
destination) and flow control device by programming the TT_FC of the CTLx
register.
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests.
Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
peripheral, assign a handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
Program the LLPx register with ‘0’.
x. For example, in the register, you can program the following:
Figure 19-7 on page
325) for channel x. For
Table 19-1 on page
326.
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