AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 387

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.6.1
32072G–11/2011
Access Types
Table 20-1.
1)
uration section at the end of this chapter.
2)
Each configuration register can be accessed in four different ways. The first address location
can be used to write the register directly. This address can also be used to read the register
value. The following addresses facilitate three different types of write access to the register. Per-
forming a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by
the operation. Performing a “clear” access, all bits written to one will be cleared. Bits written to
zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits
written to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
Offset
0xBC
0xCC
0xDC
0xB4
0xB8
0xC0
0xC4
0xC8
0xD0
0xD4
0xD8
The reset value for these registers are device specific. Please refer to the Module Config-
The reset value is undefined depending on the pin states.
Glitch Filter Enable Register
Glitch Filter Enable Register
Glitch Filter Enable Register
Glitch Filter Enable Register
Interrupt Mode Register 1
Interrupt Mode Register 1
Interrupt Mode Register 1
Interrupt Flag Register
Interrupt Flag Register
Interrupt Flag Register
Interrupt Flag Register
GPIO Register Memory Map
Register
Read/Write
Function
Toggle
Toggle
Clear
Clear
Read
Clear
Set
Set
-
-
GFERS
GFERC
GFERT
IMR1S
IMR1C
IMR1T
GFER
Name
IFRC
IFR
-
-
Read/Write
Write-Only
Write-Only
Write-Only
Write-Only
Write-Only
Write-Only
Read-Only
Write-Only
Access
-
-
Reset value
(1)
(1)
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