AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 792
AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
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- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
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28.7.2
Name:
Access Type:
Offset:
Reset Value:
• SHTIM: Sample & Hold Time
• STARTUP: Start Up Time
• PRESCAL: Prescaler Rate Selection
• SLEEP: Sleep Mode
• LOWRES: Resolution
• TRGSEL: Trigger Selection
• TRGEN: Trigger Enable
32072G–11/2011
31
23
15
0
0
0
0
1
1
1
–
–
7
–
Sample & Hold Time = (SHTIM+3) / ADCClock
Startup Time = (STARTUP+1) * 8 / ADCClock
This Time should respect a minimal value. Refer to Electrical Characteristics section for details.
ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 )
1: Sleep Mode is selected.
0: Normal Mode is selected.
1: 8-bit resolution is selected.
0: 10-bit resolution is selected.
1: The hardware trigger selected by the TRGSEL field is enabled.
0: The hardware triggers are disabled. Starting a conversion is only possible by software.
Mode Register
TRGSEL
30
22
14
0
0
1
1
0
0
1
MR
Read/Write
0x04
0x00000000
–
6
–
SLEEP
29
21
13
0
1
0
1
0
1
0
–
5
Selected TRGSEL
Internal Trigger 0, depending of chip integration
Internal Trigger 1, depending of chip integration
Internal Trigger 2, depending of chip integration
Internal Trigger 3, depending of chip integration
Internal Trigger 4, depending of chip integration
Internal Trigger 5, depending of chip integration
External trigger
LOWRES
28
20
12
–
4
PRESCAL
STARTUP
27
19
11
3
TRGSEL
26
18
10
2
SHTIM
25
17
9
1
TRGEN
24
16
8
0
792
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