AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 45
AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 45 of 1012
- Download datasheet (16Mb)
7.5.4.1
32072G–11/2011
Osc0 clock
Osc1 clock
Enabling the PLL
PLLOSC
Figure 7-3.
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency f
frequency f
if PLLDIV > 0
if PLLDIV = 0
Note:
If PLLOPT[1] field is set to 0:
If PLLOPT[1] field is set to 1:
0
1
f
f
f
f
f
f
IN
VCO
IN
VCO
PLL
PLL
Refer to Electrical Characteristics section for F
= f
= f
= f
= f
= (PLLMUL+1)/(PLLDIV) • f
= 2 • (PLLMUL+1) • f
Divider
PLL
OSC
OSC
PLLDIV
Input
VCO.
VCO
PLL with Control Logic and Filters
:
/2 • PLLDIV
/ 2
.
Fin
OSC
Divider
Output
PLLMUL
PLLOPT
PLLEN
PLL
OSC
IN
and F
VCO
frequency range.
Mask
LOCK
PLL clock
VCO
and the PLL
45
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