AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 334

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
4. After the DMACA selected channel has been programmed, enable the channel by writ-
5. Source and destination request single and burst DMACA transactions to transfer the
6. When the block transfer has completed, the DMACA reloads the SARx, DARx and
7. The DMA transfer proceeds as follows:
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx according to Row 4 as shown in
d. Write the control information for the DMA transfer in the CTLx register for channel
– i. Set up the transfer type (memory or non-memory peripheral for source and
– ii. Set up the transfer characteristics, such as:
e. Write the channel configuration information into the CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
– ii. If the hardware handshaking interface is activated for the source or destination
ing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is
enabled.
block of data (assuming non-memory peripherals). The DMACA acknowledges on
completion of each burst/single transaction and carry out the block transfer.
CTLx registers. Hardware sets the Block Complete interrupt. The DMACA then sam-
ples the row number as shown in
then the DMA transfer has completed. Hardware sets the transfer complete interrupt
and disables the channel. So you can either respond to the Block Complete or Transfer
Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is dis-
abled, to detect when the transfer is complete. If the DMACA is not in Row 1, the next
step is performed.
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
destination) and flow control device by programming the TT_FC of the CTLx
register.
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests
for the specific channel. Writing a ‘1’ activates the software handshaking interface to
handle source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
Program the LLPx register with ‘0’.
x. For example, in the register, you can program the following:
Ensure that the reload bits, CFGx. RELOAD_SR and CFGx.RELOAD_DS are
enabled.
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
Table 19-1 on page
326. If the DMACA is in Row 1,
Table 19-1 on page
326.
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