SC16C752IB48,157 NXP Semiconductors, SC16C752IB48,157 Datasheet - Page 21

• Manufacturer Part Number: SC16C752IB48,157
• Description: IC DUAL UART 64BYTE 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C752IB48,157

• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270055157; SC16C752IB48; SC16C752IB48

Philips Semiconductors
9397 750 11635
Product data
7.3 FIFO control register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs,
setting transmitter and receiver trigger levels, and selecting the type of DMA
signalling.
Table 11:
Bit
7-6
5-4
3
2
1
0
Symbol
FCR[7]
(MSB),
FCR[6]
(LSB)
FCR[5]
(MSB),
FCR[4]
(LSB)
FCR[3]
FCR[2]
FCR[1]
FCR[0]
Table 11
FIFO Control Register bits description
Rev. 04 — 20 June 2003
Description
RCVR trigger. Sets the trigger level for the RX FIFO.
TX trigger. Sets the trigger level for the TX FIFO.
FCR[5-4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
DMA mode select.
Reset TX FIFO.
Reset RX FIFO.
FIFO enable.
shows FIFO control register bit settings.
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
Logic 0 = Set DMA mode ‘0’
Logic 1 = Set DMA mode ‘1’
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Dual UART with 64-byte FIFO
SC16C752
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