SC16C752IB48,157 NXP Semiconductors, SC16C752IB48,157 Datasheet - Page 19
SC16C752IB48,157
Manufacturer Part Number
SC16C752IB48,157
Description
IC DUAL UART 64BYTE 48LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C752IB48157.pdf
(47 pages)
Specifications of SC16C752IB48,157
Number Of Channels
2, DUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270055157
SC16C752IB48
SC16C752IB48
SC16C752IB48
SC16C752IB48
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C752IB48,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 10:
Shaded bits are only accessible when EFR[4] is set.
[1]
[2]
9397 750 11635
Product data
A2 A1 A0 Register Bit 7
General Register Set
0
0
0
0
0
0
1
1
1
1
1
1
1
Special Register Set
0
0
Enhanced Register Set
0
1
1
1
1
These registers are accessible only when LCR[7] = 0.
The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
SC16C752 internal registers
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
FIFO
Rdy
DLL
DLH
EFR
Xon1
Xon2
Xoff1
Xoff2
[3]
[1]
bit 7
bit 7
0/CTS
interrupt
enable
RX
trigger
level
(MSB)
FCR[0]
DLAB
1 or
1 /4
clock
0/error in
RX FIFO
CD
bit 7
bit 7
bit 7
0
bit 7
bit 15
Auto
CTS
bit 7
bit 7
bit 7
bit 7
[4]
Table 10
[2]
Bit 6
bit 6
bit 6
0/RTS
interrupt
enable
RX trigger
level (LSB)
FCR[0]
break
control bit
TCR and
TLR
enable
THR and
TSR
empty
RI
bit 6
bit 6
bit 6
0
bit 6
bit 14
Auto RTS
bit 6
bit 6
bit 6
bit 6
lists and describes the SC16C752 internal registers.
[2]
Bit 5
bit 5
bit 5
0/Xoff
0/TX
trigger
level
(MSB)
0/CTS,
RTS
set parity parity
0/Xon
Any
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
bit 5
bit 13
Special
character
detect
bit 5
bit 5
bit 5
bit 5
Rev. 04 — 20 June 2003
[2]
[2]
Bit 4
bit 4
bit 4
0/X sleep
mode
0/TX
trigger
level
(LSB)
0/Xoff
type
select
0/enable
loop-back
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
bit 4
bit 12
Enable
enhanced
functions
[2]
bit 4
bit 4
bit 4
bit 4
[2]
[2]
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
interrupt
priority
bit 2
parity
enable
IRQ
enable
OP
framing
error
bit 3
bit 3
bit 3
0
bit 3
bit 11
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
CD
Bit 2
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
interrupt
priority
bit 1
number of
stop bits
FIFO
ready
enable
parity
error
bit 2
bit 2
bit 2
0
bit 2
bit 10
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
RI
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Dual UART with 64-byte FIFO
Bit 1
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
interrupt
priority
bit 0
word
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 1
TX FIFO B
status
bit 1
bit 9
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
DSR
SC16C752
Bit 0
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
interrupt
status
word
length
bit 0
DTR
data in
receiver
bit 0
bit 0
bit 0
TX FIFO
A status
bit 0
bit 8
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
CTS
19 of 47
Read/
Write
R
W
R/W
W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W