SC68C652BIB48,151 NXP Semiconductors, SC68C652BIB48,151 Datasheet - Page 8

• Manufacturer Part Number: SC68C652BIB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3297; 935278766151; SC68C652BIB48-S

NXP Semiconductors
6. Functional description
SC68C652B_2
Product data sheet
6.1 UART A-B functions
The SC68C652B UART is pin-compatible with the SC68C2550B UART. It provides more
enhanced features. All additional features are provided through a special enhanced
feature register.
The UART will perform serial-to-parallel conversion on data characters received from
peripheral devices or modems, and parallel-to-parallel conversion on data characters
transmitted by the processor. The complete status of each channel of the SC68C652B
UART can be read at any time during functional operation by the processor.
The SC68C652B can be placed in an alternate mode (FIFO mode) relieving the processor
of excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of
error status per byte for the receiver FIFO) and have selectable or programmable trigger
levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.
The SC68C652B has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTSn output and CTSn
input signals. Software flow control automatically controls data flow by using
programmable Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2
The UART provides the user with the capability to bidirectionally transfer information
between an external CPU, the SC68C652B package, and an external serial device. A
logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to configure, send
data, and/or receive data via UART channels A and B. Individual channel select functions
are shown in
Table 3.
CS
1
0
0
Channel selection using CS pin
A3
-
0
1
Table
3.
Rev. 02 — 2 November 2009
UART channel
none
channel A
channel B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
16
1).
SC68C652B
© NXP B.V. 2009. All rights reserved.
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