571BJC000107DG Silicon Laboratories Inc, 571BJC000107DG Datasheet - Page 28

• Manufacturer Part Number: 571BJC000107DG
• Manufacturer: Silicon Laboratories Inc

Specifications of 571BJC000107DG

• Lead Free Status / Rohs Status: Compliant

Si570/Si571
D
Revision 0.2 to Revision 0.3
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Revision 0.3 to Revision 0.31
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Revision 0.31 to Revision 1.0
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28
OCUMENT
Updated Table 1, “Recommended Operating
Conditions,” on page 5.
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Updated Table 4, “CLK± Output Levels and
Symmetry,” on page 7.
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Updated Table 5, “CLK± Output Phase Jitter
(Si570),” on page 7.
Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
Updated Table 7, “CLK± Output Period Jitter,” on
page 10.
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Updated Table 10, “Absolute Maximum Ratings,” on
page 11 to reflect the soldering temperature time at
260 ºC is 20–40 sec per JEDEC J-STD-020C.
Updated device programming procedure in Section
"3.2.3. Programming Procedure" on page 12.
Updated "7. Ordering Information" on page 24.
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Added "8. Si57x Mark Specification" on page 25.
Updated "3.2.3. Programming Procedure" on page
12.
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Corrected Freeze DCO bit location in Register 137 to
bit 4 on pages 14 and 18.
Updated " Functional Block Diagram" on page 1.
Updated Figure 1, “Si570 Detailed Block Diagram,”
on page 4.
Updated Figure 2, “Si571 Detailed Block Diagram,”
on page 4.
Updated Figure 6, “Part Number Convention,” on
page 24.
Updated Table 1, “Recommended Operating
Conditions,” on page 5.
Updated Table 3, “CLK± Output Frequency
Characteristics,” on page 6.
Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
Updated Table 12, “Programming Constraints and
Timing,” on page 12.
Device maintains stable operation over –40 to +85 ºC
operating temperature range.
Supply current specifications updated.
Updated LVDS differential peak-peak swing
specifications.
Revised period jitter specifications.
Changed ordering instructions to revision D.
Corrected Step 6 to read “bit 4”.
C
HANGE
L
IST
Rev. 1.2
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Revision 1.0 to Revision 1.1
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Revision 1.1 to Revision 1.2
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Updated Table 12, “Programming Constraints and
Timing,” on page 12.
Updated "3. Functional Description" on page 13.
Updated "3.1. Programming a New Output
Frequency" on page 13.
Updated "3.1.1. Reconfiguring the Output Clock for a
Small Change in Frequency" on page 13.
Updated "3.1.2. Reconfiguring the Output Clock for
Large Changes in Output Frequency" on page 14.
Updated “7.Ordering Information”.
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24.
Restored programming constraint information on
page 15 and in Table 12, page 12.
Clarified NC (No Connect) pin designations in Tables
13–14 on pages 22–23.
Replaced “Unfreeze to Newfreq Delay” with the
clearer terminology “Unfreeze to Newfreq Timeout”
on page 15 and in Table 12 on page 12.
Added Freeze M procedure on page 14 for
preventing output clock changes during small
frequency change multi-register RFREQ writes.
Added Freeze M, Freeze VCADC, and RST_REG
versus RECALL information to Register 135
references in "4. Serial Port Registers" on pages 17
and 20.
Updated Figure 8 and Table 16 on page 26 to
include production test sidepads. This change is for
reference only as the sidepads are raised above the
seating plane and do not impact PCB layout.
Corrected errors in Table 11 on page 12.
Updated
Figure 6, “Part Number Convention,” on page