571BJC000107DG Silicon Laboratories Inc, 571BJC000107DG Datasheet - Page 10

• Manufacturer Part Number: 571BJC000107DG
• Manufacturer: Silicon Laboratories Inc

Specifications of 571BJC000107DG

• Lead Free Status / Rohs Status: Compliant

Si570/Si571
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Table 7. CLK± Output Period Jitter
10
Phase Jitter (RMS)
for F
500 MHz
Notes:
Period Jitter*
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest K
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
4. Single ended mode: CMOS. Refer to the following application notes for further information:
OUT
requirements. See “AN266: VCXO Tuning Slope (K
rejection (PSR) advantage of Si55x versus SAW-based solutions.
“AN255: Replacing 622 MHz VCSO Device with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)”
from Phase Noise” for further information.
Parameter
Parameter
of 125 to
1,2,3
Symbol
Symbol
J
PER

J
Kv = 33 ppm/V
Kv = 45 ppm/V
Kv = 90 ppm/V
Kv = 135 ppm/V
Kv = 180 ppm/V
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Test Condition
Test Condition
Peak-to-Peak
RMS
V
Rev. 1.2
), Stability, and Absolute Pull Range (APR)” for more information.
V
Min
Min
that meets the application’s minimum APR
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0.37
0.33
0.37
0.33
0.43
0.34
0.50
0.34
0.59
0.35
1.00
0.39
Typ
Typ
14
2
Max
Max
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Units
Units
ps
ps