571BJC000107DG Silicon Laboratories Inc, 571BJC000107DG Datasheet - Page 20

• Manufacturer Part Number: 571BJC000107DG
• Manufacturer: Silicon Laboratories Inc

Specifications of 571BJC000107DG

• Lead Free Status / Rohs Status: Compliant

Si570/Si571
Register 12. Reference Frequency
Register 135. Reset/Freeze/Memory Control
Reset settings = 00xx xx00
20
Name
Name RST_REG
Type
Type
Bit
7:0
Bit
Bit
3:1
Bit
7
6
5
4
0
RFREQ[7:0]
R/W
Name
D7
D7
RST_REG
Freeze M
NewFreq
RECALL
VCADC
Freeze
Name
N/A
NewFreq
Reference Frequency.
Frequency control input to DCO.
R/W
D6
D6
Internal Reset.
0 = Normal operation.
1 = Reset of all internal logic. Output tristated during reset.
Upon completion of internal logic reset, RST_REG is internally reset to zero.
Note: Asserting RST_REG will interrupt the I
New frequency Applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied.
Freezes the M Control Word.
Prevents interim frequency changes when writing RFREQ registers.
Freezes the VC ADC Output Word.
May be used to hold the nominal output frequency of an Si571.
Always zero.
Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
Note: Asserting RECALL reloads the NVM contents in to the operating registers without
approach for starting from initial conditions.
interrupting the I
initial conditions.
Freeze M
R/W
D5
D5
Freeze VCADC
2
C state machine. It is the recommended approach for starting from
D4
Rev. 1.2
R/W
RFREQ[7:0]
D4
R/W
Function
Function
D3
2
D3
C state machine. It is not the recommended
D2
R/W
N/A
D2
D1
D1
RECALL
R/W
D0
D0