SC16C2550BIBS,157 NXP Semiconductors, SC16C2550BIBS,157 Datasheet - Page 23
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SC16C2550BIBS,157
Manufacturer Part Number
SC16C2550BIBS,157
Description
IC DUART SOT617-1
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C2550BIA44518.pdf
(43 pages)
Specifications of SC16C2550BIBS,157
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.5 V ~ 4.5 V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280309157
SC16C2550BIBS
SC16C2550BIBS
SC16C2550BIBS
SC16C2550BIBS
NXP Semiconductors
SC16C2550B_5
Product data sheet
7.8 Modem Status Register (MSR)
Table 19.
This register provides the current state of the control interface signals from the modem or
other peripheral device to which the SC16C2550B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
Table 20.
[1]
Bit
0
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
LSR[0]
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Line Status Register bits description
Modem Status Register bits description
Description
Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic 1 = data has been received and is saved in the Receive Holding Register
or FIFO
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Description
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the Loopback mode produces the state of MCR[3] (OP2).
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the Loopback mode produces the state of MCR[2] (OP1).
DSR. During normal operation, this bit is the complement of the DSR input.
During the Loopback mode, this bit is equivalent to MCR[0] (DTR).
CTS. During normal operation, this bit is the complement of the CTS input.
During the Loopback mode, this bit is equivalent to MCR[1] (RTS).
CD
RI
DSR
CTS
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C2550B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
Rev. 05 — 12 January 2009
[1]
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…continued
SC16C2550B
© NXP B.V. 2009. All rights reserved.
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