SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 37

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
Table 11.
T
with respect to ground; positive currents flow in the IC; typical values are given at V
[1]
[2]
[3]
UJA1076_2
Product data sheet
Symbol
Oscillator
f
osc
vj
=
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
−
trig(wd)2
40 °C to +150
after the start of the watchdog period (watchdog overflows).
Dynamic characteristics
Parameter
oscillator frequency
°
C; V
BAT
Fig 15. Timing test circuit for CAN transceiver
= 4.5 V to 28 V; V
…continued
C RXDC
All information provided in this document is subject to legal disclaimers.
BAT
Conditions
> V
Rev. 02 — 27 May 2010
RXDC
TXDC
V1
; V
BAT
SBC
GND
BAT
> V
V2
; R
CANH
CANL
trig(wd)1
(CANH-CANL)
High-speed CAN core system basis chip
, but not more than t
R CANH − R CANL
BAT
= 45
= 14 V; unless otherwise specified.
Ω
trig(wd)1
015aaa079
to 65
Min
460.8
trig(wd)2
after the start of the watchdog
Ω
; all voltages are defined
C CANH − C CANL
Table
, after the start of the
Typ
512
UJA1076
© NXP B.V. 2010. All rights reserved.
4); valid in watchdog
Max
563.2
37 of 47
Unit
kHz