SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 20

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
UJA1076_2
Product data sheet
6.7.1.1 Active mode
6.6.3 Voltage regulator V2
6.7.1 CAN operating modes
6.7 CAN transceiver
For short-circuit protection, a resistor needs to be connected between pins V1 and
VEXCC to allow the current to be monitored. This resistor limits the current delivered by
the external transistor. If the voltage difference between pins VEXCC and V1 reaches
V
not increase further.
The thermal performance of the transistor needs to be considered when calculating the
value of this resistor. A 3.3 Ω resistor was used with the BCP52-16
(NXP Semiconductors) employed during testing. Note that the selection of the transistor is
not critical. In general, any PNP transistor with a current amplification factor (β) of
between 60 and 500 can be used.
If an external PNP transistor is not used, pin VEXCC must be connected to V1 while pin
VEXCTRL can be left open.
One advantage of this scalable voltage regulator concept is that there are no PCB layout
restrictions when using the external PNP. The distance between the UJA1076 and the
external PNP doesn’t affect the stability of the regulator loop because the loop is realized
within the UJA1076. Therefore, it is recommended that the distance between the
UJA1076 and PNP transistor be maximized for optimal thermal distribution.
The output voltage on V1 is monitored continuously and a system reset signal is
generated if an undervoltage event occurs. A system reset is generated if the voltage on
V1 falls below the undervoltage detection voltage (V
threshold (90 % or 70 % of the nominal value) is set via the Reset Threshold Control bit
(RTHC) in the Int_Control register
interrupt) will be generated at 90 % of the nominal output voltage. The status of V1 can be
read via bit V1S in the WD_and_Status register
Voltage regulator V2 is reserved for the high-speed CAN transceiver, providing a 5 V
supply.
V2 can be activated and deactivated via the MC bits in the Mode_Control register
(Table
voltage drops below 90 % of its nominal value. The status of V2 can be read via bit V2S in
the WD_and_Status register
V2 can be deactivated (MC = 10) to allow the internal CAN transceiver to be supplied from
an external source or from V1. The alternative voltage source must be connected to pin
V2. All internal functions (e.g. undervoltage protection) will work normally.
The analog section of the UJA1076 CAN transceiver corresponds to that integrated into
the TJA1042/TJA1043. The transceiver is designed for high-speed (up to 1 Mbit/s) CAN
applications in the automotive industry, providing differential transmit and receive
capability to a CAN protocol controller.
The CAN transceiver is in Active mode when:
th(act)Ilim
5). An undervoltage warning (a V2UI interrupt) is generated when the output
, the PNP current limiting activation threshold voltage, the transistor current will
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
(Table
(Table
4) in Normal mode (V2S = 1 in all other modes).
6). In addition, an undervoltage warning (a V1UI
High-speed CAN core system basis chip
(Table
uvd
; see
4).
Table
10). The reset
UJA1076
© NXP B.V. 2010. All rights reserved.
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