82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 8

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
(current output feedback from the Frequency Select Circuit) by the
Measure Circuit. The phase difference between input reference and the
feedback signal is sent to the Storage Circuit for TIE correction. The Trigger
Circuit, depending on the value stored in the Storage Circuit, generates a
virtual reference with the phase corrected to the same position as the
previous reference. With this TIE correction mechanism, the reference is
switched without generating a step change in phase.
is performed with the TIE Control Block enabled.
by applying a logic low pulse to the TIE Control Circuit reset pin TCLR. The
reset pulse should be at least 300 ns.
periods and then turns back to Normal Mode, the TIE Control Circuit should
not be enabled. This will prevent unwanted accumulated phase change
between the input and output.
disable logic generated by the State Control Circuit) during the reference
switching, the phase of the output signal will align with the new reference,
with the phase slope limited to 5 ns per 125 s. Figure 5 shows the phase
transient results from a reference switch with the TIE Control Block
disabled.
DPLL BLOCK
Limiter, a Loop Filter, a Digital Control Oscillator and Divider Circuits.
Phase Detector (PHD)
The selected reference signal is compared with the feedback signal
Figure 4 shows the phase transient that would result if a reference switch
The value of the phase difference in the Storage Circuit can be cleared
When the IDT82V3002 primarily enters Holdover Mode for short time
If the TIE Control Block is disabled (by the TIE_en pin or TIE auto-
As shown in Figure 6, the DPLL Block consists of a Phase Detector, a
In Normal Mode, the Phase Detector compares the virtual reference
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Ref1
Ref2
Figure 5. Reference Switch with TIE Control Block Disabled
8
signal from the TIE Control Circuit with the feedback signal from the
Frequency Select Circuit, and outputs an error signal corresponding to the
phase difference between the two. This error signal is then sent to the
Limiter circuit for phase slope control.
by pins F_sel1 and F_sel0. Refer to Table 2 for details.
Detector and the Limiter are not active and the input reference signal is not
used.
Limiter
transient conditions with a maximum output phase slope of 5ns per 125
specifications, which specify the maximum phase slope of 7.6 ns per 125
Detector, limits the phase slope within 5 ns per 125 s and sends the
limited signal to the Loop Filter.
FLOCK pin high, the device will enter fast lock mode. In this case, the
Limiter is disabled, the DPLL will lock to the incoming reference within 500
ms, which is much shorter than that needed in Normal Mode.
Loop Filter
and AT&T TR624411 requirements. This Loop Filter works similarly to a first
order low pass filter with 2.1 Hz cutoff frequency for the three valid input
reference signals (8 kHz, 2.048 MHz or 1.544 MHz).
s. This well meets the AT&T TR62411 and Telcordia GR-1244-CORE
s and 81 ns per 1.326 ms, respectively.
The feedback signal can be 8 kHz, 2.048 MHz or 1.544 MHz, selected
In Freerun or Holdover Mode, the Frequency Select Circuit, the Phase
The Limiter is used for ensuring that the DPLL responds to all input
In Normal Mode, the Limiter receives the error signal from the Phase
The fast lock mode is a submode of the Normal Mode. By setting the
The Loop Filter ensures that the jitter transfer meets the ETS 300 011
The output of the Loop Filter goes directly or through the Fraction blocks
125 s
Output Clock
Input Clock
INDUSTRIAL TEMPERATURE RANGE