SC16C852LIBS,151 NXP Semiconductors, SC16C852LIBS,151 Datasheet - Page 34

• Manufacturer Part Number: SC16C852LIBS,151
• Description: IC UART DUAL W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 485r

Specifications of SC16C852LIBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: Programmable
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 1.95 V
• Supply Voltage (min): 1.65 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V
• Transmitter And Receiver Fifo Counter: Yes
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4209; 935283101151; SC16C852LIBS-S

NXP Semiconductors
SC16C852L
Product data sheet
7.8 Modem Status Register (MSR)
This register shares the same address as EFCR register. This is a read-only register and
it provides the current state of the control interface signals from the modem, or other
peripheral device to which the SC16C852L is connected. Four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
When write, the data will be written to EFCR register.
Table 23.
[1]
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
All information provided in this document is subject to legal disclaimers.
CD. During normal operation, this bit is the complement of the CDx input.
DSR. During normal operation, this bit is the complement of the DSRx input.
CTS. During normal operation, this bit is the complement of the CTSx input.
Description
Reading this bit in the loopback mode produces the state of MCR[3].
RI. During normal operation, this bit is the complement of the RIx input.
Reading this bit in the loopback mode produces the state of MCR[2].
During the loopback mode, this bit is equivalent to MCR[0].
During the loopback mode, this bit is equivalent to MCR[1].
CD
RI
DSR
CTS
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 4 — 1 February 2011
logic 0 = no CDx change (normal default condition)
logic 1 = the CDx input to the SC16C852L has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no RIx change (normal default condition)
logic 1 = the RIx input to the SC16C852L has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSRx change (normal default condition)
logic 1 = the DSRx input to the SC16C852L has changed state since the
last time it was read. A modem Status Interrupt will be generated.
logic 0 = no CTSx change (normal default condition)
logic 1 = the CTSx input to the SC16C852L has changed state since the
last time it was read. A modem Status Interrupt will be generated.
[1]
[1]
[1]
[1]
SC16C852L
© NXP B.V. 2011. All rights reserved.
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