PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 39

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PEF 24470 H V1.3

Manufacturer Part Number
PEF 24470 H V1.3
Description
IC MTSI-XL SWITCHING MQFP100
Manufacturer
Infineon Technologies
Series
SWITIr
Datasheet

Specifications of PEF 24470 H V1.3

Function
Switching IC
Interface
PCM, PLL
Number Of Circuits
1
Voltage - Supply
3.13 V ~ 3.47 V
Current - Supply
200mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-SQFP
Includes
Clock Shift, Data Rate Adaption, Multipoint Switching
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEF24470HV1.3X
SP000007617
PRELIMINARY
Figure 11
For each PCM input line the offset of time-slot zero can be adjusted in a range from 0 to
7 bit in half clock resolution before or after the PFS rising edge. For all output lines the
offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution
after the PFS rising edge.
The resolution depends on the selected data rate that means the resolution doesn’t
depend on the PDC signal.
After the reset process the bit shift is disabled for all lines. That means the time-slot 0
starts with the rising edge of PFS. All input data will be sampled with falling edge of the
selected data rate and the output data are valid with the rising edge of the selected data
rate.
4.2
The MTSI provides the programming of different data rates for all data lines. All local bus
lines can operate with 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz having data
rates of 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s and 16.384 Mbit/s.
The input and output lines are independent of each other, i.e. for a given bus line the
input and the output lines can be programmed with different data rates.
The maximum aggregate data rate supported at the input and output bus lines is
262.144 Mbit/s, with all lines operating at 16.384 Mbit/s (i.e. 16 lines x 16.384 Mbit/
s per line = 262.144 Mbit/s, as input and/or output).
Preliminary Data Sheet
D ata R ate of Selected Line
Data Rate
O ffset of
Input 0
PFS
TS0
PCM Bit Shifting
O ffset of
O ffset of
O utputs
Input 1
TS0
TS0
0
7
30
0
1
PEF 20450 / 20470 / 24470
Description of Interfaces
7
2001-11-20
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