PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 31

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PRELIMINARY
The digital PLL synchronizes the external crystal or oscillator to the selected reference
clock. The digital PLL (DPLL) will be bypassed if the selected reference signal is
>= 2.048 MHz. The input signal for the analog PLL (APLL) is 2.048 MHz in normal
operation mode. The APLL is used for multiplying the 2.048 MHz clock into a
49.152 MHz clock and to generate all clock signals for the PCM, and general purpose
clock signals.
The SWITI has an on-chip oscillator which allows the user to connect an external
16.384 MHz or 32.768 MHz crystal. Instead of using the crystal it is possible to assign a
16.384 MHz, or 32.768 MHz oscillator to the ECLKI pin.
After the power-on or hardware reset the APLL is bypassed. The APLL will be
synchronized (after approximately 750 µs) to the external crystal or external oscillator if
the command ’set external frequency’ is set. This command must be used otherwise the
internal working frequency is equal to the external input frequency and the SWITI will not
work properly. If the APLL is locked the status bit ’APLL’ in the
Note: After the reset it is necessary to program the correct crystal or oscillator
3.4.2
Features
• Low cycle-to-cycle jitter < 1 ns
• Natural frequency f
• Damping factor = 0.7
• Input Frequency = 2.048 MHz in any case
• Output Frequency = 49.152 MHz, duty-cycle = 50 %
• Rule behavior = change of output frequency in range of 0 - ±10% in response to
• phase slope of output frequency equal to phase slope of input frequency
Note: It is necessary to provide a “noise free” analog power (V
Preliminary Data Sheet
changes of input frequency
value as first programming step. Otherwise the operation frequency for the
SWITI is not correct.
the internal jitter of the APLL. These pins must be decoupled from the digital
power (VDD/VSS), see also the available Application Note “Layout Notes”.
Analog PLL (APLL)
g
= 15 kHz
22
PEF 20450 / 20470 / 24470
Architectural Description
ISTA1
DDA
register will be set.
/V
SSA
) to reduce
2001-11-20