SI3200-FS Silicon Laboratories Inc, SI3200-FS Datasheet - Page 106

IC LINEFEED INTRFC 100V 16SOIC

SI3200-FS

Manufacturer Part Number
SI3200-FS
Description
IC LINEFEED INTRFC 100V 16SOIC
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets

Specifications of SI3200-FS

Package / Case
16-SOIC (3.9mm Width)
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
110µA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Product
SLIC
Supply Voltage (min)
3.13 V
Supply Current
0.11 mA, 8.8 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3200-FS
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
SI3200-FSR
Manufacturer:
SILICON
Quantity:
11 430
Si3220/Si3225
Document Change List
Revision 0.91 to Revision 0.95
106
Table 1 on page 4
Table 3 on page 5
Table 4 on page 8
Table 5 on page 10
Table 7 on page 13
Table 8 on page 13
Table 13 on page 17
Table 14 on page 19
Figure 11 on page 24
Figure 12 on page 25
Table 18 on page 32
"Linefeed Calibration" on page 35
"Power Monitoring and Power Fault Detection" on
page 35
Table 21 on page 39
"Loop Closure Detection" on page 42
"Ground Key Detection" on page 43
1 W
Tolerance
using Si3200
Changed Si3200 thermal impedance to 55 °C/W
Changed Si3200 continuous power dissipation limit to
Modified Note 3
Added Notes 2 and 3
Modified values for IVDD1-IVDD4 and IVBAT
Added Notes 2 and 3
Modified values for IVDD1-IVDD4 and IVBAT
Modified Round Trip Group Delay to 600 µs max
Modified Monitor ADC specifications
Eliminated reference to VBAT, VTIP, and VRING in note
Changed FSYNC Jitter Tolerance to PCLK Period Jitter
Changed minimum FSYNC pulse width spec to tP/2
Changed minimum FSYNC pulse width spec to tP/2
Modified transmit path block flow
Modified names of battery supply pins
Corrected mnemonic of RLYCON register
Modified calibration sequence
Modified operating state requirement to OPEN state
Eliminated reference to Si3200 on-chip thermal diode
Corrected transistor power equations
Added note requiring connection of THERM pin when
Modified equation for PLPFxx
Modified PTHxx and PLPFxx examples
Added value for
Added PTH12 range and resolution for Si3200 mode
Modified PSUM range and resolution
Modified bit range for PLPF12-PLPF56
Modified equation for LCRLPF
τ
thermal
for Si3200
Rev. 1.0
Revision 0.95 to Revision 0.96
"Automatic Dual Battery Switching" on page 40
Figure 20 on page 41
Table 28 on page 47
"Ringing Generation" on page 46
Figure 31 on page 56
"Two-Wire Impedance Synthesis" on page 58
Table 36 on page 63
Figure 40 on page 68
"System Clock Generation" on page 67
“8-Bit Control Register Summary”, on page 90
“16-Bit RAM Address Summary”, on page 94
"Package Outline: 16-Pin ESOIC" on page 103
Table 1, “Absolute Maximum Ratings and Thermal
Information
Fixed miscellaneous typos
Added new section, "TXEQ/RXEQ Equalizer Blocks"
on page 67.
"SPI Control Interface" on page 68
Modified equation for LONGLPF
Modified equation for BATLPF
Modified circuit schematic and battery supply terminal
names
Added VRNGNG, IRNGNG, and SPEEDUPR registers
to table
Corrected equation results for sinusoidal ringing
coefficients
Added “Internal Unbalanced Ringing” functional
description
Corrected equations for trapezoidal ringing
Corrected equation for RINGOF
Corrected equations for ringing current consumption
Modified figure to show absolute TIP, RING voltages
Corrected reference to ZA and ZD blocks in Figure 11
Removed reference to 600W initial setting following
reset
Corrected LSB size for OSC1TA register
Added note for LSB size in FSK mode
Added SPI clock line to diagram
Added note describing requirement for PCLK and
FSYNC to be low at power-up
Eliminated register summary table. Refer to “AN58:
Si3220/Si3225 Programmer’s Guide”.
Eliminated RAM address summary table. Refer to
“AN58: Si3220/Si3225 Programmer’s Guide”.
Changed A1 specification to .076 REF.
Added new items
Added text.
1
,” on page 4

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