DS21Q50L+ Maxim Integrated Products, DS21Q50L+ Datasheet - Page 40

IC TXRX E1 QUAD 100-LQFP

DS21Q50L+

Manufacturer Part Number
DS21Q50L+
Description
IC TXRX E1 QUAD 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q50L+

Function
Transceiver
Interface
E1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
230mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
*
Includes
AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
6.2 CRC4 Error Counter
CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word
of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the
maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is
disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe
sync occurs at the CAS level. CRCCR1 and CRCCR2 have alternate functions.
Register Name:
Register Description:
Register Address:
Bit
Name
Name
6.3 E-Bit/PRBS Bit Error Counter
E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a
16-bit counter that records far-end block errors (FEBE), as reported in the first bit of frames 13 and 15 on
E1 lines running with CRC4 multiframe. These error count registers increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a one-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues
to count if loss-of-multiframe sync occurs at the CAS level.
Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function
is enabled. In this mode, the counter is active when the receive PRBS detector can synchronize to the
PRBS pattern. This pattern can be framed, unframed, or in any time slot. See Section
Register Name:
Register Description:
Register Address:
Bit
Name
Name
NAME
CRC15
NAME
CRC0
EB15
EB0
CRC15
CRC7
EB15
EB7
7
7
CRCCR1.7
CRCCR2.0
EBCR1.7
EBCR2.0
BIT
BIT
CRC14
CRC6
EB14
EB6
6
6
CRCCR1, CRCCR2
CRC4 Count Registers
02 Hex, 03 Hex
EBCR1, EBCR2
E-Bit Count Registers
04 Hex, 05 Hex
MSB of the 16-bit CRC4 error count
LSB of the 16-bit CRC4 error count
MSB of the 16-bit E-bit error count
LSB of the 16-bit E-bit error count
CRC13
CRC5
EB13
EB5
5
5
CRC12
CRC4
EB12
EB4
4
4
40 of 87
CRC11
CRC/3
EB11
EB3
FUNCTION
FUNCTION
3
3
CRC10
CRC2
EB10
EB2
2
2
CRC9
CRC1
EB9
EB1
1
1
CRC8
CRC0
EB8
EB0
8
0
0
for more details.

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