DS21Q50L+ Maxim Integrated Products, DS21Q50L+ Datasheet - Page 30

• Manufacturer Part Number: DS21Q50L+
• Description: IC TXRX E1 QUAD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q50L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

4.4 Remote Loopback
When CCR4.7 is set to 1, the DS21Q50 is forced into remote loopback (RLB). In this loopback, data
input through the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues
to pass through the receive framer of the DS21Q50 as it would normally and the data from the transmit
formatter is ignored
4.5 Local Loopback
When CCR4.6 is set to 1, the DS21Q50 is forced into local loopback (LLB). In this loopback, data
continues to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data
being transmitted. Data in this loopback passes through the jitter attenuator
Register Name:
Register Description:
Register Address:
Bit
Name
NAME
LIRST
RCM4
RCM3
RCM2
RCM1
RCM0
RESA
RESR
LIRST
7
BIT
7
6
5
4
3
2
1
0
RESA
(Figure
Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset that affects the
clock recovery state machine and jitter attenuator. Normally this bit is only toggled on
power-up. Must be cleared and set again for a subsequent reset.
Receive Elastic Store Align. Setting this bit from a 0 to 1 can force the receive elastic
store’s write/read pointers to a minim separation of half a frame. No action is taken if the
pointer separation is already greater or equal to half a frame. If pointer separation is less
than half a frame, the command is executed and data is disrupted. Should be toggled after
SYSCLK has been applied and is stable. Must be cleared and set again for a subsequent
align. See Section
Receive Elastic Store Reset. Setting this bit from a 0 to 1 forces the receive elastic store to
a depth of one frame. Receive data is lost during the reset. Should be toggled after
SYSCLK has been applied and is stable. Must be cleared and set again for a subsequent
reset. See Section
Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive
channel data appears in the RDS0M register. See Section
Receive Channel Monitor Bit 3
Receive Channel Monitor Bit 2
Receive Channel Monitor Bit 1
Receive Channel Monitor Bit 0. LSB of the channel decode.
6
CCR4
Common Control Register 4
15 Hex
1-1).
RESR
5
13
13
RCM4
for details.
for details.
4
30 of 87
RCM3
3
FUNCTION
RCM2
2
RCM1
6
1
(Figure
for details.
RCM0
1-1).
0