STEVAL-PCC010V2 STMicroelectronics, STEVAL-PCC010V2 Datasheet - Page 159

• Manufacturer Part Number: STEVAL-PCC010V2
• Description: BOARD EVAL FOR ST802RT1A
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-PCC010V2

• Design Resources: STEVAL-PCC010V2 BOM STEVAL-PCC010V2 Schematic
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: ST802RT1A, STM32F207
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11465

STM32F205xx, STM32F207xx
Table 89.
25-Nov-2010
Date
Document revision history (continued)
Revision
5
Update I/Os in
Added WLCSP66(64+2) package. Added note 1 related to LQFP176
on cover page.
Added trademark for
Adaptive real-time memory accelerator (ART
Updated
Added case of BOR inactivation using IRROFF on WLCSP devices in
Section 2.2.16: Power supply
Reworked
modes. Renamed PDROFF, IRROFF in the whole document.
Added
Updated LIN and IrDA features for UART4/5 in
comparison.
Table 5: STM32F20x pin and ball
added note related to the FSMC_NL pin; renamed BYPASS-REG
REGOFF, and add IRROFF pin; renamed USART4/5 UART4/5.
USART4 pins renamed UART4.
Changed V
Updated maximum HSE crystal frequency to 26 MHz.
Section 5.2: Absolute maximum
maximum values and note related to five-volt tolerant inputs in
Voltage
notes in
Updated V
conditions.
Added Note 2 and updated Maximum CPU frequency in
Limitations depending on the operating power supply
added
Added brownout level 1, 2, and 3 thresholds in
reset and power control block
Changed f
characteristics.
Changed f
and updated jitter parameters in
characteristics.
Section 5.3.16: I/O port
Table 41: I/O static
Added
Updated R
FS DC electrical
Updated V
Updated
Removed Ethernet and USB2 for 64-pin devices in
applications versus package for STM32F20xxx
Added
FS connection with external PHY” figure, updated
Figure
Doc ID 15818 Rev 6
Figure 19: Number of wait states versus fCPU and VDD
87, and
Section 2.2.20: VBAT
Note 1
A.2: Application example with regulator
characteristics. Updated I
Table 8: Current
Figure 5: Multi-AHB
Table 66: Embedded internal reference
OSC_IN
PLL_IN
DDA
REF+
Section 2.2.17: Voltage regulator
PD
SS_SA
and R
below
minimum value in
Section :
Figure 89
minimum value in
maximum value in
characteristics.
maximum value in
to V
characteristics.
PU
Table 42: Output voltage
ART accelerator.
SS
parameter description in
characteristics: updated V
, and V
Features.
characteristics.
to add STULPI01B.
operation.
matrix.
supervisor.
characteristics.
Changes
DD_SA
ratings: Updated V
Table 30: PLLI2S (audio PLL)
Table 10: General operating
definitions: Modified V
INJ(PIN)
Table 61: ADC
Table 29: Main PLL
Table 25: HSE 4-26 MHz oscillator
pin reserved for future use.
Updated
maximum values and related
to clarify regulator off
Accelerator™).
characteristics.
Table 4: USART feature
OFF, removed “OTG
Table 14: Embedded
microcontrollers.
Table 52: USB OTG
voltage.
characteristics.
Section 2.2.3:
IH
Figure
IN
Table 88: Main
Revision history
and V
range, and
minimum and
characteristics,
DD_3
Table 11:
86,
IL
in
pin, and
Table 7:
range.
159/163