STEVAL-PCC010V2 STMicroelectronics, STEVAL-PCC010V2 Datasheet - Page 157

• Manufacturer Part Number: STEVAL-PCC010V2
• Description: BOARD EVAL FOR ST802RT1A
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-PCC010V2

• Design Resources: STEVAL-PCC010V2 BOM STEVAL-PCC010V2 Schematic
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: ST802RT1A, STM32F207
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11465

STM32F205xx, STM32F207xx
Table 89.
13-Jul-2010
Date
Document revision history (continued)
Revision
4
Renamed high-speed SRAM, system SRAM.
Removed combination: 128 KBytes Flash memory in LQFP144.
Added UFBGA176 package. Added note 1 related to LQFP176
package in
Added information on ART accelerator and audio PLL (PLLI2S).
Added
Several updates on
Table 6: Alternate function
WKUP and VBUS signals removed from alternate functions and
moved to the “other functions” column in
ball
TRACESWO added in
STM32F20x pin and ball
mapping.
XTAL oscillator frequency updated on cover page, in
STM32F20x block diagram
interrupt/event controller
Updated list of peripherals used for boot mode in
modes.
Added Regulator bypass mode in
and
(regulator
Updated
backup
Added
Added SPI TI protocol in
(SPI).
Added USB OTG_FS features in
on-the-go full-speed
Updated V
Power supply
Removed DAC, modified ADC limitations, and updated I/O
compensation for 1.8 to 2.1 V range in
on the operating power supply
Added V
and power control block
Removed table Typical current consumption in Sleep mode with Flash
memory in Deep power down mode. Merged typical and maximum
current consumption sections and added
maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator
Table 16: Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory (ART
accelerator enabled) or RAM, Table 17: Typical and maximum current
consumption in Sleep mode, Table 18: Typical and maximum current
consumptions in Stop mode, Table 19: Typical and maximum current
consumptions in Standby
current consumptions in VBAT
Update
PLL spread spectrum clock generation (SSCG)
Doc ID 15818 Rev 6
definitions.
Section 5.3.4: Operating conditions at power-up / power-down
Table 4: USART feature
Note Note:
registers.
Table 29: Main PLL characteristics
BORL
Section 2.2.18: Real-time clock (RTC), backup SRAM and
OFF).
CAP_1
Table
, V
scheme.
BORM
and V
2,
in
Table 5: STM32F20x pin and ball definitions
Figure
(OTG_FS).
Section 2.2.19: Low-power
, V
Figure 4: STM32F20x block
CAP_2
characteristics.
BORH
(EXTI).
definitions, and
Section 2.2.28: Serial peripheral interface
mode, and
mapping. ADC, DAC, oscillator, RTC_AF,
12, and
and in
capacitor value to 2.2 µF in
and I
Changes
range.
mode.
comparison.
Section 2.2.33: Universal serial bus
Section 2.2.17: Voltage
Section 2.2.12: External
Table
RUSH
Table 20: Typical and maximum
Table 11: Limitations depending
Table 5: STM32F20x pin and
Table 6: Alternate function
in
87.
Table 15: Typical and
and added
Table 14: Embedded reset
characteristics.
modes.
Section 2.2.14: Boot
diagram,
Revision history
Figure 4:
Section 5.3.11:
Figure 17:
regulator,
disabled),
Table 5:
157/163
and