PIC18F1320-H/ML Microchip Technology, PIC18F1320-H/ML Datasheet - Page 70
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F1320-H/ML
Manufacturer Part Number
PIC18F1320-H/ML
Description
IC MCU 8BIT 8KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F1220/1320
REGISTER 7-1:
DS39605F-page 68
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated
0 = The write operation completed normally
WREN: Erase/Write Enable bit
1 = Allows erase/write cycles
0 = Inhibits erase/write cycles
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or write cycle.
0 = Write cycle is completed
RD: Read Control bit
1 = Initiates a memory read
0 = Read completed
EEPGD
R/W-x
Note:
(cleared by completion of erase operation)
(MCLR or WDT Reset during self-timed erase or program operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
R/W-x
CFGS
S = Settable only
-n = Value at POR
U-0
—
R/W-0
FREE
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
WREN
R/W-0
© 2007 Microchip Technology Inc.
‘0’ = Bit is cleared
R/S-0
WR
R/S-0
RD
bit 0
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